chore: release v0.2.0

[MagicalTux]

🤖 New release

• rsasm: 0.1.3 -> 0.2.0 (⚠ API breaking changes)

⚠ rsasm breaking changes

--- failure trait_method_parameter_count_changed: pub trait method parameter count changed ---

Description:
A trait method now takes a different number of parameters.
        ref: https://doc.rust-lang.org/cargo/reference/semver.html#trait-item-signature
       impl: https://github.com/obi1kenobi/cargo-semver-checks/tree/v0.50.0/src/lints/trait_method_parameter_count_changed.ron

Failed in:
  Architecture::dwarf now takes 2 instead of 1 parameters, in file /tmp/.tmp4jYfkC/rsasm/src/arch/mod.rs:1652

Changelog

0.2.0 - 2026-09-29

Other

• Fuzz against the pinned assembler, and blank what a linker fills in
• Link against qld 0.1.1
• Recompute the counts after the AArch64 and RISC-V merges
• Merge RISC-V linker relaxation and the references it defers
• Merge the AArch64 atomics, pointer authentication and memory tagging
• Merge master's m68k work into the AArch64 atomics
• Recompute the counts, and record what the two references settle
• Let the fuzzer reach the AArch64 groups the table gained
• Assemble AArch64 memory tagging, which llvm-mc was never asked for
• Assemble the AArch64 pointer-authentication instructions
• Assemble the AArch64 LSE atomics, and the pairs they name
• Assemble the AArch64 load/store exclusives and acquire/release accesses
• Assemble @SiZe on x86-64, and fold the sizes this file settles
• Recompute the counts after the modifier-refusal merge
• Merge master's m68k thread-local operands into the modifier refusal
• Refuse a relocation modifier the backend does not know in an operand
• Merge the RISC-V thread-local operands and descriptors
• Merge master's ARM coprocessor loads into the RISC-V thread-local operands
• Merge master's AArch64 and m68k work into the RISC-V thread-local operands
• Merge master's MIPS and SPARC thread-local operators into the RISC-V ones
• Assemble RISC-V's thread-local operands, in RV32 and RV64
• Recompute the counts after the ARM thread-local merge
• Merge the ARM thread-local suffixes and marks
• Recompute the counts after the thread-local and common-symbol merges
• Merge the common-symbol alignment and directive-only symbols
• Merge the PowerPC thread-local modifiers
• Give PowerPC its thread-local access models, in both word sizes
• Bring the Mach-O count up to the thread-local cases
• Merge ARM loads that name a label
• Recount the ARM row and the harness totals after the PC-relative loads
• Merge remote-tracking branch 'origin/master' into worktree-agent-ac8c8e5ff29ea168b
• Assemble ARM loads that name a label instead of a pool entry
• Merge the ARM relocation suffixes and the halves of an address
• Merge the SPARC floating-point families
• Merge the AArch64 address-group operators and the pmov index
• Merge the PowerPC branch and halfword relocation modifiers
• Merge the MIPS condition flags, conditional moves and jalx
• Merge master into the condition-flag work
• Name the floating-point condition flags, and assemble jalx
• Say why the not-generated list starts at 2
• Write down the flat-binary branch width NASM and rsasm disagree on
• List the pmov spelling among what AArch64's fuzzer drops
• Record the pmov index the AArch64 table does not have
• Say what the branch-over-a-gap cases are for, and what they found
• Say what the RISC-V program cases reach, and what they found
• Mention FUZZ_TIMEOUT in the runner's documentation
• Account for what other seeds turn up
• Say in the RISC-V fuzzer's docstring what the program cases are for
• Kill a fuzzer that hangs, and say which one it was
• Check for llvm-readobj before the fuzz job runs
• Describe the three whole-program fuzzers in the README
• Say how much the fuzz job runs and how long it takes
• Merge master: one long branch candidate, the shorter of the two
• Fold an index with no base in the NASM dialect
• Give CI three times the cases: 745,000 in under two minutes
• Record the adr expression GNU as refuses
• Account for what a heavier run turns up
• Fuzz the NASM dialect against NASM
• Narrow the RL78 truncation rule to branches
• cargo fmt
• Fuzz whole branches over a gap, not only single instructions
• List the new fuzzers in both READMEs
• Merge branch 'master' into worktree-agent-aacdb62e96c7282d5
• Fuzz the 6502 and the 8080, and expand a RISC-V branch that cannot reach
• cargo fmt
• Run the fuzzers in CI, and say how to repeat a failure
• Fuzz SuperH, RX, RL78, V850 and the Z80
• Fuzz SPARC, and read the forms its disassembler prints
• Fuzz RISC-V and MIPS, and read the aliases both references read
• Give every fuzzer one summary line and a runner to drive them from
• Refuse a wide pool entry that is not a number in the engine too
• Say what the pools hold in the README, and keep an overflow quiet
• Test the wider and narrower pool entries
• Put the pool layouts in the ARM and Thumb corpora
• Share a pool entry by what the source wrote, not by its i64
• Assemble the VFP and halfword literal loads
• Give the literal pool a per-backend layout policy
• Merge the release commit
• Reconcile the ARM pool findings with the DWARF comparison
• ARM whole-program pool fuzzer, and fixes it found

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