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feat(flow): integrate timing-routability placement and standalone diff sizing - #329
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zhaoxueyan1 wants to merge 23 commits into
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zhaoxueyan1 wants to merge 23 commits into
zhaoxueyan1 wants to merge 23 commits into
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This was referenced Oct 8, 2026
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Advance the cleaned DreamPlace PR #45 to 1277dd1300bced04c16dd0d04e8dd853004abf84. It preserves the cleaned source tree and existing clean-wheel repairs, and integrates the qualified CPU maze RRR changes from the development checkout, including coarse guidance and the complete cost schedule. Xplace is pinned to 777d1eae03e6a21a4b24801c1f7a06e4d70790aa. Positive CPU RRR remains explicit; its final completed route is used for RC evaluation. The existing installed runtime passes 14 native tests and the full 50-step fixture. Matched BM64 RRR3 returns round 3 in 27.58s, with a 16.01 percent absolute-TNS gap to the external OpenROAD GR50 reference. Build on the current ECC PR #329 head to retain CI and Sizer runtime fixes. This commit changes only the DreamPlace gitlink.
Use ten sizing/VT rounds with buffering off in the placement template and public canonical/legacy defaults, retaining direct loss as the GP carrier. Preserve explicit Pin2Pin/S5B1 selections and exercise a five-round override in the existing regression. Pin cleaned DreamPlace PR #45 at e2ddfb90205644622089ba69cadc6307fcc2adb4. Apply only the strategy diff to the latest ECC PR template, preserving its adaptive-bin, CI, and Sizer fixes. The equivalent local implementation is c84b0959909cafdb081020458b651595fe3f42c6; focused regressions passed 69 tests. Historical 13-case GR50 results support the policy choice; exact-head wheel CI and full-flow qualification remain separate.
Set cpu_pr_maze and gr_sizing_rrr_iters=3 in the canonical diff_sizing profile so initial and final GR both use the requested cost schedule. Extend the existing stage-mode regression to check the routing handoff. The independent stage uses 50 steps, padding0 and legalization. Pin cleaned DreamPlace PR #45 at 204dd3312b5f0d5a1d7411f7fcc35117d731c0d9. Its routing-handoff test and evidence record 66 focused passes and the real native S50 fixture: both GR calls3/3, final-route hashes, zero maze failures, clock gradients, master/pin updates, legalization, terminal STA and timing best-state restoration. Generic routing metadata remains RRR0. The source changes match the validated development commit 09d622b8dcce841f4e36000a8edbcdb7a157750d. No new full-case QoR or wheel CI claim.
Merge origin/main and select ecc-tools e85aa4a6000a01caa951d1ca1c3ffe29d0eb4c07, which preserves both the timing-routability feature head and main's DEF/Verilog net identity fixes. No ECC source or flow defaults are changed.
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The default RTL-to-GDS flow now runs timing/routability optimization during placement, then a distinct DreamPlace GR sizing pass before CTS. The later ECC-sizer timing optimization remains a separate stage.
Current defaults and STA qualification
The placement defaults now match the qualified optimization policy: S10B0, direct timing loss, density 0.4, padding 200 DBU, stop overflow 0.1, ordinary area reference, coefficient growth 1.0, fixed sizing-window WNS/TNS/cap/slew weights 500/5/1/1 with outer timing weight 1, smooth AAT/RAT propagation at 2 ps, and GP timing-gradient balance ratio 0.2. The placement recipe also defaults to density 0.4, so flow resolution does not restore the older 0.8 value.
The parent pins DreamPlace
e05c68367f4cdd196d4f6203fdd16c31bf3dfc71(PR #45) and ECC-Tools5083c9024238ecb83a85ea46a29b8eef5de7adaa(PR #273). They add schema-v2 max endpoint/check qualification, reject incompatible native snapshots and unsupported scalar max-path constraints, and remove stale Q arrival/slew seeds from clk-to-Q propagation. Standalone diff sizing remains S50, CPU maze RRR3, a fixed 512-bin grid, padding 0 and legalization enabled.Add
scripts/regression/placementfor frozen parallel placement plus external placement RC/GR50 STA evaluation. The timing/overflow/window controls inplacement_fixed500_smooth2.jsonnow match the production defaults. The complete profile also records the frozen CPU/thread/bin/routing and input assumptions for reproducing the earlier experiment.Current default-change validation: 100 ECC-DreamPlace integration tests, 317 DreamPlace tests plus 13 subtests, a fresh Nix/uv native rebuild on the updated ECC-Tools PR head, 3 native export/sizing/buffer-refresh tests, and the C++ qualification fixture passed. BM64 workspace preparation and effective-profile preflight also passed.
uv.lockremains unchanged. Full 13-case new-placement/GR50 QoR and exact-head remote CI are separate pending checks; older full-flow evidence below retains its stated revision scope.Latest main is merged. ECC-Tools now also includes main through
d178a690065c09adf8d04687e0f419ed84c68546, including the complete timing-graph loop cleanup. The resolved workflows retain installed CUDA smoke and the upstream Nix check jobs; parent gitlinks select the matched child heads. The merged flow/CLI/workspace/ECC-DreamPlace suites passed 250 tests, and both workflow YAML and Nix syntax checks passed. The newly enabled Nix CI exposed a staleunittest/source path; it is corrected totests/, and offline derivation evaluation from a fresh tracked-source export passed. Boost is now declared in the native build inputs, and a complete isolated Nix package build/import check passed with Python 3.13 and Torch 2.8. Full repository Ruff lint and format checks also passed (496 files). Parent artifact-dependent CI jobs need the successful wheel from this exact DreamPlace revision; their earlier missing-artifact failures did not run lint/tests.Companion PRs: DreamPlace #45, ECC-Tools #273.
What Changed
preplaceanddiff_sizingsteps, persisted workspace contracts, file chaining, and CLI parameters.diff_sizingruns DreamPlace GRsize_onlyfor 50 steps, using cpu_pr_maze + RRR3, padding 0 and legalization enabled. Its matched DEF/netlist feeds CTS.timing_opt_*controls with legacy aliases; preserve generated SDC I/O constraints and PDK overrides.Scope
S10B0 placement defaults
The placement template and canonical/legacy public parameters now select
timing_opt_sizing_rounds=10,timing_opt_buffering_enabled=0, and the existingtiming_placement_carrier=direct_loss. The current child revisions are listed above and pinned together in the parent gitlinks. Apply only the strategy changes to the latest template, retainingauto_adjust_bins=1and the published CI/Sizer fixes.The 13-case historical direct-loss/Pin2Pin × S5B0/S10B0 matrix is recorded in the DreamPlace PR. Direct-loss S10B0 had the lowest aggregate external GR50 absolute TNS, 5178.383361ns. That is prior same-input placement/GR50 evidence, not a new full-flow result for this head.
Focused configuration/window regressions: 69 passed in the development runtime and 69 passed against the PR Python sources with the existing qualified native runtime. Actual resolution confirms S10B0 in either carrier and explicit S5B1 overrides. The independent diff_sizing stage continues to use its 50-step GR sizing profile. Exact-head wheel/package/full-flow CI is tracked separately from the historical validation below.
Runtime And Packaging Impact
The new stages have separate persisted directories and artifacts. Standard CI resolves native wheels at the exact child gitlink commits; default DreamPlace package builds use ECC without OpenROAD.
Validation
The previous full-flow CI evidence below applies to ECC ad698be with DreamPlace d9323146b837285ed3cc0e838c425d404f9b873a. The new DreamPlace gitlink is validated separately as described below.
All repair work is in an independent clone; the original development workspace is preserved.
chipcompiler/andtest/passed.Local acceptance used the unmodified published CPU wheels, verified against their source revisions, and an isolated Sizer build. Remote acceptance used the PyInstaller bundle with the exact child revisions and Sizer CI artifact
37740318841ata694bb1. The unmodified DreamPlace wheel also passed the 137-test CPU smoke and replayed the two captured USB RC failures. Both former hold failures, BM64 and y_huff, passed the unchanged strict post-route signoff gates. The extra remote permission-test skip is expected in the root container. No new CUDA or 13-case QoR claim is made.Clean DreamPlace source integration
The DreamPlace gitlink selects the complete, cleaned implementation in openecos-projects/ecc-dreamplace#45 at
204dd3312b5f0d5a1d7411f7fcc35117d731c0d9. Its cleaned foundation11a537a519d84d2e814d33e3fd4b4c7bede07046has the same source tree as the locally validated cleanup treef421905e9b1088242e84e50caa3648bee022094b. The current head adds the optional CPU maze RRR integration described below while preserving the cleanup; the current ECC update also aligns placement-window defaults while retaining the existing adaptive-bin, CI and Sizer fixes.e71c2d3c: https://github.com/openecos-projects/ecc/actions/runs/37774915599 tracked independently from the historical full-flow results above and from the current RRR update.diff_sizing default: CPU maze RRR3
ECC's independent diff_sizing stage now selects
gpugr_backend=cpu_pr_mazeandgr_sizing_rrr_iters=3. It performs 50 sizing steps with padding0 and legalization. The initial GR snapshot and the final GR on committed legal geometry both use RRR3; optimizer steps consume the frozen differentiable RC snapshot between those calls. Placement remains S10B0 + direct loss. Generic GR parameter metadata remains zero; this is a stage-owned default.Validation: 66 focused tests passed, and 66 passed against the cleaned PR Python sources using the qualified installed native runtime. The real clocked native S50 fixture completed all 50 steps; both GR calls requested/completed3/3 and exported the last completed state with zero maze failures. Real clock gradients, master/pin geometry changes, legalization, terminal STA, and independent combined timing-loss best-state restoration passed. See
docs/plans/evidence/diff-sizing-rrr3-default.jsonfor source/runtime/artifact hashes.This is synthetic native lifecycle qualification. No new BM64/multi-case QoR or exact-head wheel CI result is claimed.
CPU maze RRR dependency update
Current ECC head:
e2ad516fc55ae6f55e6f4546486a0e6ec4140f13. The CPU RRR integration is included alongside the S10B0 default-policy update, on top of the published ECC CI/Sizer fixes. DreamPlace retains the cleaned PR source and pins Xplace777d1eae03e6a21a4b24801c1f7a06e4d70790aa.CPU maze RRR is the default backend for the independent diff_sizing stage and is explicitly selectable elsewhere. It uses deterministic parallel batches and coarse/fine search, completes remaining changing cost passes after intermediate non-improvement, and returns the final route for RC evaluation. Positive CPU RRR uses cpu_pr_maze. ECC diff_sizing selects three passes by default; generic GR metadata retains zero.
Publication-worktree interface/native regressions also passed: 31 passed, 6 subtests passed, using the cleaned PR Python source and the existing qualified installed native runtime. This check is not a fresh full-wheel build.
Local qualification includes 14 installed native tests and the full 50-step S50 fixture. Matched original-DEF BM64 RRR3 completes/returns round3 in 27.58s; native-RC/OpenROAD read-only STA WNS/TNS is -2.594371/-899.165955ns (16.01% absolute-TNS gap to external GR50). See DreamPlace's committed schedule evidence for hashes, reused reference provenance, and remaining alignment/performance limits. Historical full-flow CI above does not certify this new parent/child head; fresh CI is tracked independently.
Companion PRs and gitlinks
cc920dc0dd5876b6d3bcf21053ad12c30e980ce4204dd3312b5f0d5a1d7411f7fcc35117d731c0d9Router dependency: zhaoxueyan1/Xplace#1.
Sizer runtime:
a694bb1dd25e8f8d761296e96c735c77fd11db68, openecos-projects/ecc-sizer#8. The workflow matches its exacthead_shaand successful CI status. This revision preserves committed IO geometry during GR and sets zero wire RC for preplace.Merge order: Xplace, ecc-tools, and ecc-sizer, then ecc-dreamplace, then ECC. If a child is squash-merged, update the parent gitlink before merging.
Checklist