Issues

• Multi-GPU timing runs read stale data: L1 caches don't route remote addresses to RDMA (Akita v5.0.0-beta.10)

  sarchlab/mgpusim#310 · Filter by author syifan opened on Oct 8, 2026

• NVIDIA: tracking issue for timing-model simplifications

  enhancementnvidia
  sarchlab/mgpusim#303 · Filter by author syifan opened on Sep 25, 2026

• NVIDIA: decide the memory path from the trace, not from fuzzy opcode matching

  bugnvidia
  sarchlab/mgpusim#302 · Filter by author syifan opened on Sep 25, 2026

• NVIDIA: model shared and local memory separately from the global cache hierarchy

  bugnvidia
  sarchlab/mgpusim#301 · Filter by author syifan opened on Sep 25, 2026

• NVIDIA: add the missing PolyBench conv2d benchmark

  sarchlab/mgpusim#300 · Filter by author syifan opened on Sep 24, 2026

• NVIDIA: honor TRACE_LINEINFO when parsing instruction traces

  sarchlab/mgpusim#299 · Filter by author syifan opened on Sep 24, 2026

• NVIDIA: replay all active-lane memory addresses and coalesce cache-line requests

  sarchlab/mgpusim#298 · Filter by author syifan opened on Sep 24, 2026

• Reduce visualization trace (-trace-vis) file size and collection overhead

  sarchlab/mgpusim#283 · Filter by author syifan opened on Jun 26, 2026

• Make concurrent-kernel dispatch policy configurable

  sarchlab/mgpusim#282 · Filter by author syifan opened on Jun 26, 2026

• CDNA3/gfx942 emulator: no global atomics — blocks faithful calibration of atomic-dependent benchmarks (npb_ep, gramschmidt, …)

  enhancement
  sarchlab/mgpusim#278 · Filter by author syifan opened on Jun 25, 2026
  1

• Simulation for LLM workload in MGPUSim

  sarchlab/mgpusim#238 · Filter by author jiangaojie opened on Dec 1, 2025

• No fixed latency for page migration?

  enhancementhelp wantedpage migration
  sarchlab/mgpusim#235 · Filter by author ch1y0q opened on Nov 12, 2025
  1

• Add maxWG tracer

  sarchlab/mgpusim#234 · Filter by author DX990307 opened on Oct 30, 2025

• Support for visTraceXXX and disableAkitaRTM Arguments in MGPUSim

  Feature

  sarchlab/mgpusim#233 · Filter by author EnzeXu opened on Oct 30, 2025

• Questions Regarding Cache Latency Configuration in MGPUSim

  sarchlab/mgpusim#225 · Filter by author MaxKev1n opened on Oct 22, 2025

• Seeking Guidance on HSACO File Compilation

  questionworkloads
  sarchlab/mgpusim#223 · Filter by author jianqiao673 opened on Oct 13, 2025
  5

• No RDMA traffic count when -use-unified-memory is enabled

  bug
  sarchlab/mgpusim#220 · Filter by author ch1y0q opened on Sep 21, 2025
  5

• Remove all the synchronous version of the AMD driver APIs

  sarchlab/mgpusim#217 · Filter by author syifan opened on Sep 8, 2025

• -trace-mem is not working

  bug
  Bug

  sarchlab/mgpusim#202 · Filter by author syifan opened on Aug 20, 2025

• Remove Async execution at Runer and Driver

  sarchlab/mgpusim#198 · Filter by author syifan opened on Jul 28, 2025

• Report memory system port traffic

  help wanted
  Feature

  sarchlab/mgpusim#185 · Filter by author syifan opened on Jun 9, 2025

• Can fullyconnectedLayer becomes a benchmark on its own?

  bug
  sarchlab/mgpusim#176 · Filter by author chz05 opened on May 20, 2025
  1

• matrixmultiplication fail the verification when X != Y

  bug
  sarchlab/mgpusim#160 · Filter by author Yfeng-44 opened on Mar 23, 2025
  1

• Question about allocateUnifiedGPUPage() allocation strategy in device.go

  bug
  sarchlab/mgpusim#115 · Filter by author Taoger-Xu opened on Nov 12, 2024

• Separate GMMU Page Table on MGPUSim V3

  sarchlab/mgpusim#113 · Filter by author DX990307 opened on Nov 11, 2024