"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
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Jul 9, 2023 - Verilog
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digital-system-design
Here are 75 public repositories matching this topic...
All my projects, homework, hand writings, course slides and anything I have learned and done during my studies at IUT😊. feel free to give it a ⭐=)
algorithms data-structures microprocessor operating-systems compiler-design proteus advanced-programming codevision automata-theory basic-programming database-lab computer-networks signals-and-systems architecutre network-lab digital-system-design
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Jan 18, 2025 - Jupyter Notebook
Single Cycle Processor written in SystemVerilog for executing machine code of RISC-V ISA
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Apr 23, 2023 - SystemVerilog
Final Project for Digital Systems Design Course, Fall 2020
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Jul 20, 2022 - Verilog
Implementation of a low-pass FIR filter in Verilog HDL.
matlab digital-signal-processing verilog-hdl fir-filters digital-system-design digital-systems-design low-pass-filters
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Apr 12, 2024 - Verilog
Fixed Point FPGA-based Hardware Implementation of a 32-tap Low Pass FIR Filter for Audio Applications
fpga verilog digital-signal-processing verilog-hdl audio-processing equalizer filter-design xilinx-vivado fir-filters audio-equalizer digital-system-design digital-signal-processing-filters digital-systems-design
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Dec 28, 2024 - Verilog
CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] | SE Semester III | Computer Engineering
computer-science engineering vhdl computer-engineering textbooks boolean-algebra digital-systems study-materials digital-electronics digital-logic-design vhdl-coursework university-of-mumbai digital-system-design digital-logic-design-lab ameythakur amey megasatish reference-books ameyarc amey-thakur
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Sep 5, 2026
My activity in digital systems
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Apr 8, 2023
Direct Digital Synthesizer for Generating Sine Waves using Verilog HDL
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Mar 29, 2024 - Verilog
Carrier is an acoustic OFDM communication system with a SystemVerilog transmitter on a Basys 3 FPGA and a software receiver in Python/C. Data travels from a host PC via UART to the FPGA, through a PCM5102 DAC and speaker as sound, and is decoded from a microphone on the receiving machine.
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Aug 23, 2026 - SystemVerilog
Implementation and verification of a hardware-based controller for a three-phase induction motor on an FPGA — Bachelor's Thesis [UPC-TTU, 2019]
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Apr 19, 2021 - VHDL
Digital Systems Design - Spring 2023 - Sharif University of Technology
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Apr 2, 2024 - Verilog
3-stage RISC-V Pipelined Processor with interrupt CSR support
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Jun 2, 2023 - SystemVerilog
Implementation of a FIFO structure for Digital Systems | Written in Verilog HDL
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Mar 26, 2024 - Verilog
This GitHub repository Consists of materials, code samples, documentation, and valuable resources related to the Information Technology (IT) Department at the National Institute of Technology Karnataka (NITK). 📚 Resource Library 💻 Code Samples 🗂️ Project Repositories
automata code projects assignment questions discrete-mathematics database-management quiz papers compiler-design object-oriented-programming data-structures-and-algorithms computer-networks signals-and-systems web-technologies probability-and-statistics digital-system-design design-and-analysis-of-algorithms opearting-system
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Jun 1, 2024 - Jupyter Notebook
Verilog implementation of the basic structure of an FPGA
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May 22, 2024 - Verilog
FIFO Buffer Implemented in VHDL
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Oct 12, 2025 - VHDL
Digital Logic Design (DLD) is a fundamental subject for the engineering students worldwide. Well, many students find it difficult to design the digital circuits properly while pursuing the DLD course in colleges or universities. Therefore, I will try to assist those students by sharing my lab works with them.
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Dec 10, 2020
Binary Adder, Subtractor, Multiplier, Divider in VHDL with FPGA board.
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Apr 19, 2025 - VHDL
Lab projects using Verilog HDL
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Apr 26, 2022 - Verilog
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