uvm-register-model

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Here are 9 public repositories matching this topic...

rggen / rggen

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Code generation tool for control and status registers

Updated Sep 11, 2026
Ruby

SystemRDL / PeakRDL

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Control and status register code generator toolchain

asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model

Updated Sep 1, 2026
Python

SystemRDL / PeakRDL-uvm

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Generate UVM register model from compiled SystemRDL input

asic fpga eda uvm registers uvm-ral-model uvm-register-model

Updated Nov 25, 2025
Python

Claude Code / Codex CLI skill that scaffolds a runnable UVM testbench (APB / AHB-Lite / AXI4-Lite + generic-bus fallback) from an IP spec and register table, with a UVM-sequence flow for DV and a tb_api:: task BFM for DE.

Updated Jul 14, 2026
Python

rggen / rggen-sample-testbench

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vhdl verilog systemverilog uvm uvm-ral-model uvm-register-model

Updated Jul 15, 2026
VHDL

rggen / rggen-sv-ral

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UVM RAL class package for RgGen

systemverilog uvm ral uvm-ral-model uvm-register-model

Updated Jan 7, 2026
SystemVerilog

AlphaLyrae0 / UVM_RAL_DPI_C_Example

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Example of C/C++ register access with name through UVM RAL

verilog systemverilog uvm dpi-c uvm-ral-model uvm-register-model

Updated Mar 15, 2026
SystemVerilog

retsureyy / AXI-lite---UART-bridge-UVM-testbench

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UVM testbench for an AXI4-Lite to UART bridge with multi-agent environment, UVM RAL, functional coverage, SVA, negative testing, and Makefile-based regression.

uart systemverilog uvm axi4-lite uvm-register-model functional-coverage uvm-verification systemverilog-test-bench uvm-testbench

Updated Sep 13, 2026
SystemVerilog

Khallil973 / uvm-ral-register-verification

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UVM-based register verification environment using explicit predictor

systemverilog uvm testbench predictor uvm-ral-model uvm-register-model uvm-verification uvm-testbench designverification

Updated Mar 9, 2026
SystemVerilog

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uvm-register-model

Here are 9 public repositories matching this topic...

rggen / rggen

SystemRDL / PeakRDL

SystemRDL / PeakRDL-uvm

gokeshenzhen / gen-tb-skill

rggen / rggen-sample-testbench

rggen / rggen-sv-ral

AlphaLyrae0 / UVM_RAL_DPI_C_Example

retsureyy / AXI-lite---UART-bridge-UVM-testbench

Khallil973 / uvm-ral-register-verification

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