arithmetic/sub: declare the missing cout port

[kroening]

Summary

arithmetic/sub/rtl/sub.v computes

assign {cout, out[DW-1:0]} = a[DW-1:0] - b[DW-1:0];

but cout is never declared: it isn't a port, and there's no
wire/reg declaration for it either. This is invalid Verilog (an
undeclared identifier used on an lvalue), caught by any tool that
checks for undeclared identifiers -- e.g. ebmc reports
unknown identifier cout while type-checking, and rejects the module.

Fix

Add cout as an output port, mirroring the sibling add module's
cin/cout convention: a - b is computed as a (DW+1)-bit
operation, with the extra bit carrying the borrow/carry-out.

How found

Found via ebmc's parse/elaborate pass over the benchmark suite,
reported at https://diffblue.github.io/hw-cbmc/logikbench/.