#

amba-axi

Here are 12 public repositories matching this topic...

taichi-ishitani / tvip-axi

AMBA AXI VIP

vip systemverilog uvm axi amba axi4 amba-axi

Updated Oct 1, 2026
SystemVerilog

taichi-ishitani / tnoc

Network on Chip Implementation written in SytemVerilog

systemverilog uvm noc axi amba network-on-chip axi4 amba-axi

Updated Aug 27, 2022
SystemVerilog

kumarrishav14 / AXI

VIP for AXI Protocol

uvm sv asic-verification amba-axi design-verification

Updated May 24, 2022
SystemVerilog

sean-galloway / RTLDesignSherpa

This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.

rtl system-verilog dma crossbar cocotb amba-axi amba-apb fabric-generator

Updated Oct 1, 2026
SystemVerilog

RISMicroDevices / OpenNCB

Open-source Non-coherent CHI Bridge (CHI SN-F to AXI-4 bridge)

bus chisel chisel3 soc chi axi amba protocol-converter axi4 amba-axi soc-design amba-chi protocol-bridge

Updated Oct 9, 2024
Scala

OpenXiangShan / OpenNCB

Open-source Non-coherent CHI Bridge (CHI SN-F to AXI-4 bridge)

bus chisel chisel3 soc axi4 amba-axi amba-chi protocol-bridge

Updated Sep 18, 2025
Scala

krailis / zynq-axi-tutorial

A tutorial on the usage of AXI4-Lite and AXI4-Stream Interfaces on HW Accelerators generated through High-Level Synthesis (HLS)

tcl vivado petalinux high-level-synthesis axi4-lite amba-axi axi4-stream-interfaces

Updated Jul 15, 2016
Tcl

aayush062026 / pcie-transaction-layer

PCIe Transaction Layer: TLP arbiter, ECRC/LCRC reference RTL over AMBA AXI.

verilog systemverilog pcie tlp amba-axi rtl-design protocol-ip transaction-layer

Updated Aug 8, 2026

ansh07verma / AXI4-Lite-Protocol-Checker

SystemVerilog AXI4-Lite protocol verification environment featuring a 5-channel monitor, associative-array scoreboard, 13 SVA assertions, functional coverage closure, back-pressure testing, and negative protocol testbench.

verification assertions scoreboard vivado systemverilog digital-design sva asic-verification hardware-verification axi4-lite amba-axi xsim rtl-design functional-coverage

Updated Sep 1, 2026
SystemVerilog

KaidenHsu / SOPC-System-Design

homework and labs for "SOPC Design Practice and FPGA System Design (2026 Spring)" in NSYSU, Taiwan

fpga driver amba-axi ai-accelerators digital-ip

Updated May 28, 2026
Verilog

k-vijay-kumar / Vlsi-Protocols

On-chip and peripheral communication protocols

i2c spi uart vlsi amba-axi amba-apb amba-ahb

Updated Sep 27, 2026

Archit-y / axi-lite-uvm-verification

UVM verification environment for an AXI4-Lite slave — 4/4 tests passing, 0 errors, up to 100% functional coverage

verification verilog systemverilog uvm axi amba amba-axi design-verification

Updated Aug 14, 2026
SystemVerilog

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