A Fast, Low-Overhead On-chip Network
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Updated
Oct 1, 2026 - SystemVerilog
A Fast, Low-Overhead On-chip Network
Network on Chip Simulator
A Chisel RTL generator for network-on-chip interconnects
Open-source alert management for NOC/DevOps teams: one queue for Grafana, Datadog, Zabbix, Uptime Kuma and GCP alerts — with ownership, mute policies, root-cause analysis and insights. Self-hosted, one container.
Network on Chip Implementation written in SytemVerilog
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
Deprecated NOC mirror. Switch to the official one
GenieACS UI Panel External
HLS for Networks-on-Chip
Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
Cycle Accurate Network-on-Chip Simulator
Sound and browser notification the moment a new Zabbix problem appears, using the browser session you're already logged into. Multi-instance, no token required, nothing hardcoded. PT/EN/ES.
openENOC is an open-source Ethernet-based NoC for scalable MPSoC systems, using Layer-2 frame switching to connect CPUs, accelerators and peripherals for crypto, AI and edge computing.
Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research
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